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Data Sheet, Rev.1.0, April 2008
BTS4175SGA
Smart High-Side Power Switch
Automotive Power
BTS4175SGA
1 2 3 3.1 3.2 3.3 4 4.1 4.2 4.3 5 5.1 5.2 5.3 5.4 6 6.1 6.2 6.3 6.4 6.5 6.6 7 7.1 7.2 7.2.1 7.2.2 7.3 8 8.1 8.2 9 9.1 10 11
Overview 3 Block Diagram 5 Pin Configuration 6 Pin Assignment 6 Pin Definitions and Functions 6 Voltage and Current Definition 7 General Product Characteristics 8 Absolute Maximum Ratings 8 Functional Range 9 Thermal Resistance 9 Power Stage 10 Output ON-State Resistance 10 Turn ON / OFF Characteristics 10 Inductive Output Clamp 11 Electrical Characteristics Power Stage 13 Protection Mechanisms 14 Loss of Ground Protection 14 Undervoltage Protection 14 Overvoltage Protection 14 Reverse Polarity Protection 15 Overload Protection 15 Electrical Characteristics Protection Functions 17 Diagnostic Mechanism 18 ST Pin 18 ST Signal in Case of Failures 18 Diagnostic in Open Load, Channel OFF 18 ST Signal in case of Over Temperature 20 Electrical Characteristics Diagnostic Functions 21 Input Pin 22 Input Circuitry 22 Electrical Characteristics 22 Application Information 23 Further Application Information 23 Package Outlines 24 Revision History 25
Data Sheet
2
Rev.1.0, 2008-04-29
Smart High-Side Power Switch
BTS4175SGA
1
* * * * * * * * * *
Overview
Fit for 12V and 24V application One Channel device Very Low Stand-by Current CMOS Compatible Inputs Electrostatic Discharge Protection (ESD) Optimized Electromagnetic Compatibility Logic ground independent from load ground Very Low Leakage Current from OUT to the load in OFF state Green Product (RoHS compliant) AEC Qualified
Basic Features
PG-DSO-8-24
Description The BTS4175SGA is a single channel Smart High-Side Power Switch. It is embedded in a PG-DSO-8-24 package, providing protective functions and diagnostics. The power transistor is built by a N-channel power MOSFET with charge pump. The device is monolithically integrated in Smart technology. It is specially designed to drive Relay, R5W lamp or LED in the harsh automotive environment. Table 1 Parameter Operating voltage range Over voltage protection Maximum ON State resistance at Tj = 150C Nominal load current Minimum current limitation Standby current for the whole device with load Maximum reverse battery voltage Diagnostic Feature * * * * Open load in OFF Feedback of the thermal shutdown in ON state Feedback of the current limitation Diagnostic feedback with open drain output Electrical Parameters (short form) Symbol Value 6V .... 52V 62V 350m 1.3A 6A 18A 52V
VSOP VS (AZ) RDS(ON) IL (nom) IL_SCR IS(off)
-Vs(REV)
Type BTS4175SGA Data Sheet
Package PG-DSO-8-24 3
Marking 4175SGA Rev.1.0, 2008-04-29
BTS4175SGA
Overview Protection Functions * * * * * * * Short circuit protection Overload protection Current limitation Thermal shutdown Overvoltage protection (including load dump) with external resistor Loss of ground and loss of battery protection Electrostatic discharge protection (ESD)
Application * All types of relays, lamps and resistive loads
Data Sheet
4
Rev.1.0, 2008-04-29
BTS4175SGA
Block Diagram
2
Block Diagram
VS internal power supply voltage sensor over temperature gate control & charge pump T clamp for inductive load over current switch off OUT
IN E SD protection ST
driver logic
open load detection
GND
Block diagram .emf
Figure 1
Block diagram for the BTS4175SGA
Data Sheet
5
Rev.1.0, 2008-04-29
BTS4175SGA
Pin Configuration
3
3.1
Pin Configuration
Pin Assignment
GND IN OUT ST
1 2 3 4
8 7 6 5
VS VS VS VS
Figure 2
Pin Configuration
3.2
Pin 1 2 3 4 5, 6, 7, 8
Pin Definitions and Functions
Symbol GND IN OUT Function Ground; Ground connection Input channel; Input signal. Activate the channel in case of logic high level Output; Protected High side power output channel Diagnostic feedback; of channel. Open drain. Battery voltage; Design the wiring for the simultaneous max. short circuit current and also for low thermal resistance
ST
VS
Data Sheet
6
Rev.1.0, 2008-04-29
BTS4175SGA
Pin Configuration
3.3
Voltage and Current Definition
Figure 3 shows all terms used in this data sheet, with associated convention for positive values.
VS IIN VIN VS IN
IS VD S OUT IL
VOU T IST V ST ST
GND
R GND
I GN D Voltage and current convention single avec diag.vsd
Figure 3
Voltage and current definition
Data Sheet
7
Rev.1.0, 2008-04-29
BTS4175SGA
General Product Characteristics
4
4.1
General Product Characteristics
Absolute Maximum Ratings
Absolute Maximum Ratings 1)
TJ = 25C; (unless otherwise specified)
Pos. Voltages 4.1.1 4.1.2 4.1.3 Supply voltage Reverse polarity Voltage Parameter Symbol Limit Values Min. Max. 52 52 36 V V V - - Unit Conditions
VS - VS(REV)
- 0 0
Supply voltage for short circuit protection Vbat(SC)
RECU = 20m, RCable=16m/m, LCable=1H/m,
l = 0 or 5m 2)
Input pins 4.1.4 4.1.5 4.1.6 4.1.7 4.1.8 Voltage at INPUT pins Current through INPUT pins Load current Power dissipation (DC), Inductive load switch off energy dissipation, Single pulse
see Chapter 6
VIN IIN
| IL |
-10 -5 - - -
16 5 IL(LIM) 1.5 125
V mA A W mJ
- - -
Power stage
PTOT EAS
TA=85C, Tj <150C Tj=150C, VS=13.5V, IL = 1A
Currents Temperatures 4.1.9 4.1.10 4.1.11 4.1.12 Junction Temperature Storage Temperature ESD Resistivity IN pin ESD Resistivity all other pins
Tj Tstg VESD VESD
-40 -55 -1 -5
150 150 1 5
C C kV kV
- - HBM3) HBM3)
ESD Susceptibility
1) Not subject to production test, specified by design 2) In accordance to AEC Q100-012 and AEC Q101-006 3) ESD susceptibility HBM according to EIA/JESD 22-A 114B
Note: Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Note: Integrated protection functions are designed to prevent IC destruction under fault conditions described in the data sheet. Fault conditions are considered as "outside" normal operating range. Protection functions are not designed for continuous repetitive operation.
Data Sheet
8
Rev.1.0, 2008-04-29
BTS4175SGA
General Product Characteristics
4.2
Pos. 4.2.1
Functional Range
Parameter Operating Voltage Symbol Min. Limit Values Max. 52 V 6 Unit Conditions
VSOP
VIN = 4.5V, RL = 47, VDS < 0.5V
-
4.2.2 4.2.3 4.2.4
Undervoltage shutdown Operating current Standby current for whole device with load
VSUV IGND IS(OFF)
- - -
5.5 2 15 18
V mA A
VIN = 5V Tj <85C Tj = 150C, RL = 47, VIN = 0V
Note: Within the functional range the IC operates as described in the circuit description. The electrical characteristics are specified within the conditions given in the related electrical characteristics table.
4.3
Pos. 4.3.1 4.3.2
Thermal Resistance
Parameter Junction to Soldering Point Junction to Ambient: Channel active Symbol Min. Limit Values Typ. - 83 Max. 15 - K/W K/W - -1) with 6cm cooling area1) - Unit Conditions
RthJS RthJA
1) Not subject to production test, specified by design
Data Sheet
9
Rev.1.0, 2008-04-29
BTS4175SGA
Power Stage
5
5.1
Power Stage
Output ON-State Resistance
The power stage is built by an N-channel vertical power MOSFET (DMOS) with charge pump.
The ON-state resistance RDS(ON) depends on the supply voltage as well as the junction temperature Tj. Figure 4 shows the dependencies for the typical ON-state resistance. The behavior in reverse polarity is described in Chapter 6.4.
400 350 300
1000 900 800 700
Rdson (m )
200 150 100 50
Rdson (m )
250
600 500 400 300 200 100
0
0
10 0
12 0
14 0
-2 0
-4 0
01234
5 6 7 8 9 10 11 12 13 14 15 16 17 18 Battery voltage (V)
60
Junction tem perature (C)
80
20
40
0
Rdson.vsd
Figure 4
Typical ON-state resistance
A high signal (See Chapter 8) at the input pin causes the power DMOS to switch ON with a dedicated slope, which is optimized in terms of EMC emission.
5.2
Turn ON / OFF Characteristics
IN
Figure 5 shows the typical timing when switching a resistive load.
V IN_H_min VIN_L_max
t dV/dt OFF tON
V OUT 90% VS 70% VS dV/dt ON 30% VS 10% VS
t OFF t
Switching times.vsd
Figure 5
Turn ON/OFF (resistive) timing
Data Sheet
10
Rev.1.0, 2008-04-29
BTS4175SGA
Power Stage
5.3
Inductive Output Clamp
When switching OFF inductive loads with high side switches, the voltage VOUT drops below ground potential, because the inductance intends to continue driving the current. To prevent the destruction of the device due to high voltages, there is a voltage clamp mechanism implemented that keeps the negative output voltage at a certain level (VS-VDS(AZ)). Please refers to Figure 6 and Figure 7 for details. Nevertheless, the maximum allowed load inductance is limited.
VS
IN LOGIC V BAT GND VIN OUT L, RL IL
V DS
VOUT
Output clamp.vsd
Figure 6
Output clamp
IN
t VOUT VS t VS-VDS(AZ) tpeak IL
t
Switching an inductance.vsd
Figure 7
Switching in inductance timing
Maximum Load inductance During demagnetization of inductive loads, energy has to be dissipated in the BTS4175SGA. This energy can be calculated with following equation:
V S - V DS ( AZ ) LRL x IL E = V DS ( AZ ) x ------- x --------------------------------------- + ln --------------------------------------- + I L V S - V DS ( AZ ) RL RL
Following equation simplifies under the assumption of RL = 0. Data Sheet 11 Rev.1.0, 2008-04-29
BTS4175SGA
Power Stage
VS 2 1 E = -- x LI x 1 - ------------------------------------------ 2 V S - V DS ( AZ ) )
The energy, which is converted into heat, is limited by the thermal design of the component. See Figure 8 for the maximum allowed energy dissipation.
1800 1600 1400 1200 EAS(mJ) 1000 800 600 400 200 0 0 0,5 Load current (A) 1 1,5
EAS.vsd
Figure 8
Maximum energy dissipation single pulse, Tj,Start = 150 C; VS = 13.5V
Data Sheet
12
Rev.1.0, 2008-04-29
BTS4175SGA
Power Stage
5.4
Electrical Characteristics Power Stage
Electrical Characteristics: Power stage
VS = 13.5 V, Tj = -40 C to +150 C,(unless otherwise specified). Typical values are given at Tj = 25C
Pos. 5.4.1 Parameter ON-state resistance per channel Symbol Min. Limit Values Typ. 175 Max. - m Tj=25C1), - Unit Conditions
RDS(ON)
IL = 1A, VIN= 5V,
See Figure 4 - 5.4.2 5.4.3 5.4.4 5.4.5 5.4.6 5.4.7 5.4.8 5.4.9 Nominal load current Drain to Source clamping Voltage 280 - 63 - 0.7 0.9 80 80 200 5 2 2 180 200 350 - A V A V/s V/s s s k Tj=150C
IL(nom) VDS(AZ) IL(OFF)
dV/dtON -dV/dtOFF
1.3 59 - - - - -
VDS(AZ) = VS-VOUT
Output leakage current Slew rate ON 10% to 30% VOUT Slew rate OFF 70% to 40% VOUT Turn-ON time to 90% VS Includes propagation delay Turn-OFF time to 10% VS Includes propagation delay Internal output pull down
TA=85C1), Tj <150C1) IDS = 4mA2) VIN=0V RL=47, Vs=13.5V
See Figure 5
tON tOFF RPD
VOUT(OL) = 4V
1) Not subject to production test, specified by design 2) Voltage is measured by forcing IDS.
Data Sheet
13
Rev.1.0, 2008-04-29
BTS4175SGA
Protection Mechanisms
6
Protection Mechanisms
The device provides embedded protective functions. Integrated protection functions are designed to prevent the destruction of the IC from fault conditions described in the data sheet. Fault conditions are considered as "outside" normal operating range. Protection functions are designed for neither continuous nor repetitive operation.
6.1
Loss of Ground Protection
In case of loss of the module ground, where the load remains connected to ground, the device protects itself by automatically turning OFF (when it was previously ON) or remains OFF, regardless of the voltage applied on IN pin. In that case, a maximum I(OUTGND) can flow out of the output.
6.2
Undervoltage Protection
Below VSOP_min, the under voltage mechanism is met. If the supply voltage is below the under voltage mechanism, the device is OFF (turns OFF). As soon as the supply voltage is above the under voltage mechanism, then the device can be switched ON and the protection functions are operational.
6.3
Overvoltage Protection
There is a clamp mechanism for over voltage protection. To guarantee this mechanism operates properly in the application, the current in the zener diode ZDAZ has to be limited by a ground resistor. Figure 9 shows a typical application to withstand overvoltage issues. In case of supply greater than VS(AZ), the power transistor switches ON and the voltage across logic section is clamped. As a result, the internal ground potential rises to VS - VS(AZ). Due to the ESD zener diodes, the potential at pin IN rises almost to that potential, depending on the impedance of the connected circuitry. Integrated resistors are provided at the IN pin to protect the input circuitry from excessive current flow during this condition.
VS VBAT IN R ST ST R IN LOGIC ZD AZ
OUT
ZD ESD
GND R GND
Overvoltage protection single with diag.vsd
Figure 9
Over voltage protection with external components
Data Sheet
14
Rev.1.0, 2008-04-29
BTS4175SGA
Protection Mechanisms In the case the supply voltage is in between of VS(SC) max and VDS(AZ), the output transistor is still operational and follow the input. If the channel is in ON state, parameters are no longer warranted and lifetime is reduced compared to normal mode. This specially impacts the short circuit robustness, as well as the maximum energy EAS the device can handle.
6.4
Reverse Polarity Protection
In case of reverse polarity, the intrinsic body diode causes power dissipation. The current in this intrinsic body diode is limited by the load itself. Additionally, the current into the ground path and the logical pins has to be limited to the maximum current described in Chapter 4.1, sometimes with an external resistor. Figure 10 shows a typical application. The RGND resistor is used to limit the current in the zener protection of the device. Resistors RIN and RST is used to limit the current in the logic of the device and in the ESD protection stage. The recommended value for RGND is 150, for RST 0/1= 15k. In case the over voltage is not considered in the application, RGND can be replaced by a Shottky diode.
VccC
Micro controller (e.g. XC22xx)
RSTPU VS ST R IN
Zdbody
R ST
VBAT -VDS(REV) OUT
IN
ZDESD GND
I L(nom)
RGND
Reverse Polarity single with diag.vsd
Figure 10
Reverse polarity protection with external components
6.5
Overload Protection
In case of overload, or short circuit to ground, the BTS4175SGA offers two protections mechanisms. Current limitation At first step, the instantaneous power in the switch is maintained to a safe level by limiting the current to the maximum current allowed in the switch IL(LIM). During this time, the DMOS temperature is increasing, which affects the current flowing in the DMOS. Thermal protection At thermal shutdown, the device turns OFF and cools down. A restart mechanism is used, after cooling down, the device restarts and limits the current to IL(SCR). Figure 11 shows the behavior of the current limitation as a function of time.
Data Sheet
15
Rev.1.0, 2008-04-29
BTS4175SGA
Protection Mechanisms
IN
IL IL(LIM) tm
t
IL(SCr)
t ST
TdST(+)
t
Current limitation with diag full . vsd
Figure 11
Current limitation function of the time
Data Sheet
16
Rev.1.0, 2008-04-29
BTS4175SGA
Protection Mechanisms
6.6
Electrical Characteristics Protection Functions
Electrical Characteristics: Protection
VS = 13.5 V, Tj = -40 C to +150 C. Typical values are given at Tj = 25C
Pos. Parameter Symbol Min. Reverse polarity 6.6.1 Drain source diode voltage during reverse polarity Over voltage protection -VDS(REV) - 600 - mV Limit Values Typ. Max. Unit Conditions
TJ = 150C VOUT > VS Is = 4mA Tj = -40C, Tj = 25C, Tj = 150C VS < 40V1), VS > 40V1)
-1) - 1)
Overvoltage 6.6.2 6.6.3
VS(AZ)
62 - - 4 - 150 -
- - 6.5 - 6.5 4.5 - 10
- 9 - - - - -
V A
Overload condition Initial peak short circuit current limit IL(LIM) (pin 5 to 3) VS = 20V; tm = 150s Repetitive short circuit current limitation Thermal shutdown temperature Thermal shutdown hysteresis
6.6.4 6.6.5 6.6.6
IL(SCR) TjSC
TJT
A C K
1) Not subject to production test, but specified by design
Data Sheet
17
Rev.1.0, 2008-04-29
BTS4175SGA
Diagnostic Mechanism
7
7.1
Diagnostic Mechanism
ST Pin
For diagnosis purpose, the BTS4175SGA provides a status pin.
BTS4175SGA status pin is an open drain, active low circuit. Figure 12 shows the equivalent circuitry. As long as no "hard" failure mode occurs (Short circuit to GND / Over temperature or open load in OFF), the signal is permanently high, and due to a required external pull-up to the logic voltage will exhibit a logic high in the application. A suggested value for the RPU ST is 15k. .
VccC
R PU ST
ST
R ST
Channel 0 Diagnostic Logic
ZD ESD
GND
ST pin full diag.vsd
Figure 12
Status output circuitry
7.2
Table 3
ST Signal in Case of Failures
ST pin truth table IN L H L H L H OUT L H > V(OL) H L L ST H H L1) H H L
Table 3 gives a quick reference for the logical state of the ST pin during device operation. Device operation Normal operation Open Load channel Over temp channel
1) L if potential at the output exceeds the Openload detection voltage
7.2.1
Diagnostic in Open Load, Channel OFF
For open load diagnosis in OFF-state, an external output pull-up resistor (ROL) is recommended. For calculation of the pull-up resistor value, the leakage currents and the open load threshold voltage VOL(OFF) has to be taken into account. Figure 13 gives a sketch of the situation and Figure 14 shows the typical timing diagram.
Ileakage defines the leakage current in the complete system, including IL(OFF) (see Chapter 5.4) and external
leakages e.g due to humidity, corrosion, etc... in the application. To reduce the stand-by current of the system, an open load resistor switch SOL is recommended.
Data Sheet
18
Rev.1.0, 2008-04-29
BTS4175SGA
Diagnostic Mechanism If the channel is OFF, the output is no longer pulled down by the load and VOUT voltage rises to nearly VS. This is recognized by the device as open load. The voltage threshold is given by VOL(OFF). In that case, the ST signal is switched to a logical low VSTL.
Vbat SOL
BTS4175SGA
VS R OL
OUT OL comp. GND
I LOFF
R PD
Ileakage VOL(OFF )
RGND
Rleakage
Open Load in OFF .vsd
Figure 13
Open load detection in OFF electrical equivalent circuit
IN t
V OUT VOL(OFF) IL
t
ST V ST(HIGH) VST(LOW)
t
t
Diagnostic In Open load full diag.vs
Figure 14
ST in open load condition
Data Sheet
19
Rev.1.0, 2008-04-29
BTS4175SGA
Diagnostic Mechanism
7.2.2
ST Signal in case of Over Temperature
In case of over temperature, the junction temperature reaches the thermal shutdown temperature TjSC. In that case, the ST signal is stable and remains to toggling between VST(L) and VST(H). Figure 15 gives a sketch of the situation.
IN t
V OUT
ST
t
t T JSC T JSC TJ
t
Diagnostic In Overload full toggling.vs
Figure 15 .
Sense signal in overtemperature condition
Data Sheet
20
Rev.1.0, 2008-04-29
BTS4175SGA
Diagnostic Mechanism
7.3
Electrical Characteristics Diagnostic Functions
Electrical Characteristics: Diagnostics
VS = 13.5 V, Tj = -40 C to +150 C, (unless otherwise specified) Typical values are given at Vs = 13.5V, Tj = 25C
Pos. Parameter Symbol Min. Load condition threshold for diagnostic 7.3.1 7.3.1 ST pin 7.3.2 7.3.3 Status output (open drain) High level; Zener limit voltage Status output (open drain) Low level Open Load detection threshold in OFF state1) Short circuit detection voltage Limit Values Typ. 3.0 2.8 6.1 - Max. 4.0 - - 0.6 V V V V Unit Conditions
VOL(OFF) VOUT(SC) VST (HIGH) VST (LOW)
- - 5.4 -
VIN = 0V
-3)
IST = +1,6mA2),
Zener Limit voltage
IST =+1,6mA2)
Diagnostic timing 7.3.4 7.3.5 Status invalid after positive input tdST(+) slope Status invalid after negative input slope - - 120 250 160 400 s s -3) -
tdST(-)
1) External pull up resistor required for open load detection in OFF state 2) If ground resistor RGND is used, the voltage drop across this resistor has to be added 3) Not subject to production test, specified by design
Data Sheet
21
Rev.1.0, 2008-04-29
BTS4175SGA
Input Pin
8
8.1
Input Pin
Input Circuitry
The input circuitry is CMOS compatible. The concept of the Input pin is to react to voltage transition and not to voltage threshold. With the Schmidt trigger, it is impossible to have the device in an un-defined state, if the voltage on the input pin is slowly increasing or decreasing. The output is either OFF or ON but cannot be in an linear or undefined state. The input circuitry is compatible with PWM applications. Figure 16 shows the electrical equivalent input circuitry. The pull down current source ensures the channel is OFF with a floating input.
RI II ESD
Input circuitry.vsd
IN
To driver's logic
Figure 16
Input pin circuitry
8.2
Electrical Characteristics
Electrical Characteristics: Diagnostics
VS = 13.5 V, Tj = -40 C to +150 C, Typical values are given at Vs = 13.5V, Tj = 25C
Pos. Parameter Symbol Min. INput pins characteristics 8.2.1 8.2.2 8.2.3 8.2.4 8.2.5 8.2.6 Low level input voltage High level input voltage Input voltage hysteresis Low level input current High level input current Input resistance Limit Values Typ. - - 0.4 - - 3.5 Max. 0.8 - - 25 25 5 V V V A A k -1) -1) -2) Unit Conditions
VIN(L) VIN(H) VIN(HYS) IIN(L) IIN(H) RI
- 2.2 - 1 3 2
VIN= 0,7V VIN= 5V
See Figure 16
1) If ground resistor RGND is used, the voltage drop across this resistor has to be added 2) Not subject to production test, specified by design
Data Sheet
22
Rev.1.0, 2008-04-29
BTS4175SGA
Application Information
9
Application Information
Note: The following information is given as a hint for the implementation of the device only and shall not be regarded as a description or warranty of a certain functionality, condition or quality of the device.
VDD RPUST Vdd OUT Microcontroller (e.g. XC22xx) IN RST GND GND R GND
Application example single avec diag.vsd
VDD
VBAT VBAT_SW Vs IN OUT ROL
R IN
ST
IS
Figure 17
Application diagram with BTS4175SGA
Note: This is a very simplified example of an application circuit. The function must be verified in the real application.
9.1
*
Further Application Information
For further information you may visit http://www.infineon.com/
Data Sheet
23
Rev.1.0, 2008-04-29
BTS4175SGA
Package Outlines
10
Package Outlines
0.33 0.08 x 45
1.75 MAX. 0.1 MIN. (1.5)
4 -0.21)
8 MAX.
+0.05 -0.01
1.27 0.41 +0.1 -0.05 8 5
0.1
C
6 0.2
0.64 0.25
0.2 M A C x8
Index Marking 1
4
5 -0.21)
1)
A
Index Marking (Chamfer) Does not include plastic or metal protrusion of 0.15 max. per side
Figure 18 PG-DSO-8-24 (Plastic Dual Small Outline Package)
Green Product (RoHS compliant) To meet the world-wide customer requirements for environmentally friendly products and to be compliant with government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e Pbfree finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020).
Data Sheet
24
0.2
Rev.1.0, 2008-04-29
BTS4175SGA
Revision History
11
Version 1.0
Revision History
Date 2008-03-12 Changes Creation of the data sheet
Data Sheet
25
Rev.1.0, 2008-04-29
Edition 2008-04-29 Published by Infineon Technologies AG 81726 Munich, Germany (c) 2008 Infineon Technologies AG All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the nearest Infineon Technologies Office. Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.

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